Information or data can be stored relatively inexpensively in various magnetic or optical mass-storage devices such as tapes, disks or drums. These devices are slow, non-volatile, and only provide for access to large blocks of data. Silicon-based random access memory (RAM) is significantly faster, provides for random byte-by-byte access to data, but is volatile, and more expensive. The difference in speed is often several orders of magnitude.
It is therefore common practice in the computer industry to mass-store data in magnetic or optical mass-storage devices, transfer the data to RAM for use or modification, and then transfer the data back to mass-storage devices.
Due to the speed difference between RAM and mass-storage devices, a computer process is significantly delayed when more data is needed from a mass-storage device. Several methods are used to minimize such delays.
One common approach is the use of a cache memory. Such a memory is usually silicon based and part of the mass-storage controller. When the computer requests data from the mass-storage device, the requested data is fetched from the mass-storage device along with a prefetch of more data than requested. The prefetched data is loaded into the cache memory (located in the mass-storage controller) in hopes that the data that is subsequently requested will already be in the cache memory. The requested data is also retained assuming that it is likely to be used again. Each subsequent request for data is checked first against the cache memory before it is fetched from the mass-storage device. Data that is already in the cache memory can be supplied to the computer much faster than data that must be fetched from a mass-storage device.
Dynamic RAM memory can only accept data (write) or give data (read) at a given time. It is therefore important that the cache memory be able to read and write as quickly as possible so it is available for other requests. The cache memory spends a majority of its time in communication with mass-storage devices because mass-storage devices are so much slower than RAM.
Prior art: U.S. Pat. No. 4,181,937--Hattori et al., "Data Processing System Having an Intermediate Buffer Memory"; U.S. Pat. No. 4,268,907--Porter et al., "Cache Unit Bypass Apparatus"; U.S. Pat. No. 4,298,929--Capozzi, "Integrated Multilevel Storage Hierarchy for a Data Processing System with Improved Channel to Memory Write Capability"; and U.S. Pat. No. 4,464,712--Fletcher, "Second Level Cache replacement Method and Apparatus".